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low skew, 2/4,4/5/6, differential-to-3.3v lvpecl clock generator 87339i-11 data sheet ?2016 integrated device technology, inc revision b january 25, 2016 1 g eneral d escription the 87339i-11 is a low skew, high performance differential-to-3.3v lvpecl clock generator/divider. the 87339i-11 has one differential clock input pair. the clk, nclk pair can accept most standard differential input levels. the clock enable isinternally synchronized to eliminate runt pulses on theoutputs during asynchronous as- sertion/deassertion of the clock enable pin. guaranteed output and part-to-part skew charac- teristics make the 87339i-11 ideal for clock distribution applications demanding well defined performance and repeatability. f eatures ? dual 2, 4 differential 3.3v lvpecl outputs; dual 4, 5, 6 differential 3.3v lvpecl outputs ? one differential clk, nclk input pair ? clk, nclk pair can accept the following differential input levels: lvds, lvpecl, lvhstl, sstl, hcsl ? maximum clock input frequency: 1ghz ? translates any single ended input signal (lvcmos, lvttl, gtl) to lvpecl levels with resistor bias on nclk input ? output skew: 35ps (maximum) ? part-to-part skew: 385ps (maximum) ? bank skew: bank a - 20ps (maximum) bank b - 20ps (maximum) ? propagation delay: 2.1ns (maximum) ? lvpecl mode operating voltage supply range: v cc = 3v to 3.6v, v ee = 0v ? available in lead-free (rohs 6) package b lock d iagram p in a ssignment 87339i-11 20-lead tssop 6.50mm x 4.40mm x 0.92 package body g package top view 20-lead soic, 300mil 7.5mm x 12.8mm x 2.25mm package body m package top view
87339i-11 data sheet ?2016 integrated device technology, inc revision b january 25, 2016 2 t able 2. p in c haracteristics t able 1. p in d escriptions symbol parameter test conditions minimum typical maximum units c in input capacitance 4 pf r pullup input pullup resistor 51 k r pulldown input pulldown resistor 51 k number name type description 1, 8, 20 v cc power positive supply pins. 2 nclk_en input pulldown clock enable. lvcmos / lvttl interface levels. see table 3. 3 div_selb0 input pulldown selects divide value for bank b outputs as described in table 3. lvcmos / lvttl interface levels. 4 clk input pulldown non-inverting differential clock input. 5 nclk input pullup inverting differential clock input. 6 reserved reserve reserve pin. 7 mr input pulldown active high master reset. when logic high, the internal dividers are reset causing the true outputs qx to go low and the inverted outputs nqx to go high. when logic low, the internal dividers and the outputs are enabled. lvcmos / lvttl interface levels. 9 div_selb1 input pulldown selects divide value for bank b outputs as described in table 3. lvcmos / lvttl interface levels. 10 div_sela input pulldown selects divide value for bank a outputs as described in table 3. lvcmos / lvttl interface levels. 11 v ee power negative supply pin. 12, 13 nqb1, qb1 output differential output pair. lvpecl interface levels. 14, 15 nqb0, qb0 output differential output pair. lvpecl interface levels. 16, 17 nqa1, qa1 output differential output pair. lvpecl interface levels. 18, 19 nqa0, qa0 output differential output pair. lvpecl interface levels. note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values.
87339i-11 data sheet ?2016 integrated device technology, inc revision b january 25, 2016 3 t able 3. c ontrol i nput f unction t able inputs outputs mr nclk_en div_sela div_selb0 div_selb1 qa0, qa1 nqa0, nqa1 qb0, qb1 nqb0, nqb1 1 x x x x low high low high 01 x x x not switch- ing not switching not switch- ing not switching 00 0 0 02244 00 0 0 12255 00 0 1 02266 00 0 1 12255 00 1 0 04444 00 1 0 14455 00 1 1 04466 00 1 1 14455 note: after nclk_en switches, the clock outputs stop switching following a rising and falling input clock edge. f igure 1a. mr t iming d iagram f igure 1b. n clk_en t iming d iagram
87339i-11 data sheet ?2016 integrated device technology, inc revision b january 25, 2016 4 t able 4a. p ower s upply dc c haracteristics , v cc = 3.3v0.3v, t a = -40c to 85c t able 4b. lvcmos / lvttl dc c haracteristics , v cc = 3.3v0.3v, t a = -40c to 85c t able 4c. d ifferential dc c haracteristics , v cc = 3.3v0.3v, t a = -40c to 85c symbol parameter test conditions minimum typical maximum units v cc positive supply voltage 3.0 3.3 3.6 v i ee power supply current 105 ma symbol parameter test conditions minimum typical maximum units v ih input high voltage 2 v cc + 0.3 v v il input low voltage -0.3 0.8 v i ih input high current nclk_en, mr, div_sela, div_selbx v in = v cc = 3.6v 150 a i il input low current nclk_en, mr, div_sela, div_selbx v in = 0v, v cc = 3.6v -5 a symbol parameter test conditions minimum typical maximum units i ih input high current nclk v in = v cc = 3.6v 5 a clk v in = v cc = 3.6v 150 a i il input low current nclk v in = 0v, v cc = 3.6v -150 a clk v in = 0v, v cc = 3.6v -5 a v pp peak-to-peak input voltage 0.15 1.3 v v cmr common mode input voltage; note 1, 2 v ee + 0.5 v cc - 0.85 v note 1: for single ended applications, the maximum input voltage for clk, nclk is v cc + 0.3v. note 2: common mode voltage is de? ned as v ih . a bsolute m aximum r atings supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5 v outputs, i o continuous current 50ma surge current 100ma package thermal impedance, ja 20 lead tssop 73.2c/w (0 lfpm) 20 lead soic 46.2c/w (0 lfpm) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress speci? cations only. functional operation of product at these conditions or any conditions beyond those listed in the dc characteristics or ac charac- teristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability.
87339i-11 data sheet ?2016 integrated device technology, inc revision b january 25, 2016 5 t able 5. ac c haracteristics , v cc = 3.3v0.3v, t a = -40c to 85c t able 4d. lvpecl dc c haracteristics , v cc = 3.3v0.3v, t a = -40c to 85c symbol parameter test conditions minimum typical maximum units f clk clock input frequency 1 ghz t pd propagation delay; note 1 clk to q (diff) 1.6 2.1 ns t sk(o) output skew; note 2, 5 15 35 ps t sk(b) bank skew; note 3, 5 bank a 10 20 ps bank b 10 20 ps t sk(pp) part-to-part skew; note 4, 5 385 ps t s setup time nclk_en to clk 350 ps t h hold time clk to nclk_en 100 ps t rr reset recovery time 400 ps t pw minimum pulse width clk 550 ps t r / t f output rise/fall time 20% to 80% 100 600 ps odc output duty cycle 48 52 % all data taken with outputs 4. note 1: measured from the differential input crossing point to the differential output crossing point. note 2: de? ned as skew between outputs at the same supply voltage and with equal load conditions. measured at the output differential cross points note 3: de? ned as skew within a bank of outputs and with equal load conditions. note 4: de? ned as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. using the same type of inputs on each device, the outputs are measured at the differential cross points. note 5: this parameter is de? ned in accordance with jedec standard 65. symbol parameter test conditions minimum typical maximum units v oh output high voltage; note1 v cc - 1.4 v cc - 0.9 v v ol output low voltage; note 1 v cc - 2.0 v cc - 1.7 v v swing peak-to-peak output voltage swing 0.6 1.0 v note 1: outputs terminated with 50 to v cc - 2v.
87339i-11 data sheet ?2016 integrated device technology, inc revision b january 25, 2016 6 p arameter m easurement i nformation p art - to -p art s kew b ank s kew o utput r ise /f all t ime d ifferential i nput l evel o utput s kew 3.3v o utput l oad ac t est c ircuit p ropagation d elay o utput d uty c ycle /p ulse w idth /p eriod
87339i-11 data sheet ?2016 integrated device technology, inc revision b january 25, 2016 7 a pplication i nformation figure 2 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref = v cc /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the ratio f igure 2. s ingle e nded s ignal d riving d ifferential i nput the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. fout and nfout are low impedance follower outputs that generate ecl/lvpecl compatible outputs. therefore, termi- nating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 3a and 3b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. t ermination for lvpecl o utputs f igure 3b. lvpecl o utput t ermination f igure 3a. lvpecl o utput t ermination w iring the d ifferential i nput to a ccept s ingle e nded l evels of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. for example, if the input clock swing is only 2.5v and v cc = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. v_ref r1 1k c1 0.1u r2 1k single ended clock input clk nclk vcc
87339i-11 data sheet ?2016 integrated device technology, inc revision b january 25, 2016 8 f igure 4c. clk/ n clk i nput d riven by 3.3v lvpecl d river f igure 4b. clk/ n clk i nput d riven by 3.3v lvpecl d river f igure 4d. clk/ n clk i nput d riven by 3.3v lvds d river 3.3v r1 50 r3 50 zo = 50 ohm lvpecl zo = 50 ohm hiperclocks clk nclk 3.3v input r2 50 zo = 50 ohm input hiperclocks clk nclk 3.3v r3 125 r2 84 zo = 50 ohm 3.3v r4 125 lvpecl r1 84 3.3v d ifferential c lock i nput i nterface the clk /nclk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 4a to 4e show interface examples for the clk/nclk input driven by the most common driver types. the input interfaces suggested here are f igure 4a. clk/ n clk i nput d riven by lvhstl d river examples only. please consult with the vendor of the driver component to con? rm the driver termination requirements. for example in figure 4a, the input termination applies for lvh- stl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. 1.8v r2 50 input lvhstl driver ics hiperclocks r1 50 lvhstl 3.3v zo = 50 ohm zo = 50 ohm hiperclocks clk nclk f igure 4e. clk/ n clk i nput d riven by 3.3v lvpecl d river with ac c ouple zo = 50 ohm r3 125 hiperclocks clk nclk 3.3v r5 100 - 200 3.3v r2 84 3.3v r6 100 - 200 input r5,r6 locate near the driver pin. zo = 50 ohm r1 84 r4 125 c2 lvpecl c1 zo = 50 ohm r1 100 3.3v lvds_driv er zo = 50 ohm receiv er clk nclk 3.3v
87339i-11 data sheet ?2016 integrated device technology, inc revision b january 25, 2016 9 p ower c onsiderations this section provides information on power dissipation and junction temperature for the 87339i-11. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the 87339i-11 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 0.3v = 3.6v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i cc_max = 3.6v * 105ma = 378mw ? power (outputs) max = 30mw/loaded output pair if all outputs are loaded, the total power is 4 * 30mw = 120mw total power _max (3.6v, with all outputs switching) = 378mw + 120mw = 498mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for the devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming a moderate air ? ow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6c/w per table 6a below . therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.498w * 66.6c/w = 118.1c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air ? ow , and the type of board (single layer or multi-layer). 0 200 500 single-layer pcb, jedec standard test boards 114.5c/w 98.0c/w 88.0c/w multi-layer pcb, jedec standard test boards 73.2c/w 66.6c/w 63.5c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. ja by velocity (linear feet per minute) table 6a. thermal resistance ja for 20-pin tssop, forced convection ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 83.2c/w 65.7c/w 57.5c/w multi-layer pcb, jedec standard test boards 46.2c/w 39.7c/w 36.8c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. table 6b. thermal resistance ja for 20-pin soic, forced convection
87339i-11 data sheet ?2016 integrated device technology, inc revision b january 25, 2016 10 3. calculations and equations. lvpecl output driver circuit and termination are shown in figure 5. t o calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of v cc - 2v. ? for logic high, v out = v oh_max = v cc_max ? 0.9v (v cc_max - v oh_max ) = 0.9v ? for logic low, v out = v ol_max = v cc_max ? 1.7v (v cc_max - v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cc_max - 2v))/r l ] * (v cc_max - v oh_max ) = [(2v - (v cc_max - v oh_max )) /r l ] * (v cc_max - v oh_max ) = [(2v - 0.9v)/50 ] * 0.9v = 19.8mw pd_l = [(v ol_max ? (v cc_max - 2v))/r l ] * (v cc_max - v ol_max ) = [(2v - (v cc_max - v ol_max )) /r l ] * (v cc_max - v ol_max ) = [(2v - 1.7v)/50 ] * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30mw f igure 5. lvpecl d river c ircuit and t ermination
87339i-11 data sheet ?2016 integrated device technology, inc revision b january 25, 2016 11 r eliability i nformation t ransistor c ount the transistor count for 87339i-11 is: 1745 compatible with mc10ep139, mc100ep139 t able 7b. ja vs . a ir f low soic t able ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 83.2c/w 65.7c/w 57.5c/w multi-layer pcb, jedec standard test boards 46.2c/w 39.7c/w 36.8c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. 0 200 500 single-layer pcb, jedec standard test boards 114.5c/w 98.0c/w 88.0c/w multi-layer pcb, jedec standard test boards 73.2c/w 66.6c/w 63.5c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. ja by velocity (linear feet per minute) t able 7a. ja vs . a ir f low tssop t able
87339i-11 data sheet ?2016 integrated device technology, inc revision b january 25, 2016 12 p ackage o utline - m s uffix for 20 l ead soic t able 8b. p ackage d imensions reference document: jedec publication 95, ms-013, mo-119 symbol millimeters minimum maximum n20 a -- 2.65 a1 0.10 -- a2 2.05 2.55 b 0.33 0.51 c 0.18 0.32 d 12.60 13.00 e 7.40 7.60 e 1.27 basic h 10.00 10.65 h 0.25 0.75 l 0.40 1.27 0 8 p ackage o utline - g s uffix for 20 l ead tssop t able 8a. p ackage d imensions reference document: jedec publication 95, mo-153 symbol millimeters min max n20 a -- 1.20 a1 0.05 0.15 a2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 d 6.40 6.60 e 6.40 basic e1 4.30 4.50 e 0.65 basic l 0.45 0.75 0 8 aaa -- 0.10
87339i-11 data sheet ?2016 integrated device technology, inc revision b january 25, 2016 13 t able 9. o rdering i nformation part/order number marking package shipping packaging temperature 87339agi-11lf ics7339ai11l 20 lead ?lead free? tssop tube -40c to +85c 87339agi-11lft ics7339ai11l 20 lead ?lead free? tssop tape and reel -40c to +85c 87339ami-11lf ics7339ai11l 20 lead ?lead free? soic tube -40c to +85c 87339AMI-11LFT ics7339ai11l 20 lead ?lead free? soic tape and reel -40c to +85c
87339i-11 data sheet ?2016 integrated device technology, inc revision b january 25, 2016 14 revision history sheet rev table page description of change date at1 1 2 pin assignment - changed pin 6, ?nc? to ?reserved?. pin description table - corrected pin 6 to read reserved to coordinate with pin assignment. 3/10/05 a t9 1 13 features section - corrected output skew and part-to-part skew bullets. ordering information table - added lead-free note. 4/12/05 a t9 13 ordering information table - added lead-free markings 12/19/07 bt9 13 15 updated datasheet?s header/footer with idt from ics. removed ics pre? x from part/order number column. added contact page. 8/2/10 bt9 1 13 remove ics from part numbers where needed. features section - removed reference to leaded package. ordering information - remove quantity from tape and reel. deleted lf note below the table. updated header and footer. 1/25/16
87339i-11 data sheet disclaimer integrated device technology, inc. (idt) reserves the right to modify the products and/or speci cations described herein at any time, without notice, at idt's sole discretion. performance speci cations and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the sam e way when installed in customer products. the information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of i dt's products for any particular purpose, an implied warranty of merchantability, or non-infringe- ment of the intellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt's products are not intended for use in applications involving extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expect- ed to signi cantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are trademarks or registered trademarks of idt and its subsidiaries in the u nited states and other countries. other trademarks used herein are the property of idt or their respective third party owners. for datasheet type de nitions and a glossary of common terms, visit www.idt.com/go/glossary . copyright ?2016 integrated device technology, inc. all rights reserved. corporate headquarters 6024 silver creek valley road san jose, ca 95138 usa www.idt.com sales 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com/go/sales tech support www.idt.com/go/support

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